MODELING OF FINFET DEVICES AT CRYOGENIC TEMPERATURES

Cryogenic operation of advanced CMOS is fundamental for scalable quantum computing interfaces and cryogenic RF electronics, yet prevailing device models inadequately capture transistor behaviour far below ambient temperature. This thesis presents an empirical compact modeling framework for FinFET devices that extends the well-established Angelov model formulation at room temperature to accurately reproduce DC drain current characteristics from ambient down to cryogenic temperatures. The proposed model introduces temperature aware modifications that capture the dominant trends shaping DC I–V behaviour while ensuring smooth parameter evolution across the full temperature range. The approach is validated on a commercial 16-nm FinFET technology, demonstrating very good agreement with measured characteristics across bias conditions, temperatures, and maintaining numerical robustness and compact model efficiency. The formulation supports predictive DC modeling that if integrated with model of the nonlinear dynamic behaviour of the transistor, can be suitable for RF design of cryogenic integrated circuits. Beyond reproducing DC I–V curves, the methodology provides a practical path for technology bring up and PDK development at cryogenic temperatures, facilitating design portability and performance optimization for cryo-CMOS circuits. Collectively, the results establish a reliable, implementation ready model foundation for RF applications in quantum computing integrated circuits using advanced FinFET nodes.