In this work an analog Integrate-And-Fire Neuron is described and implemented in 7 nm FinFET technology. The circuit operates at a power supply voltage of 750 mV and features an operational-amplifier-based comparator to set an explicit spiking threshold voltage. A capacitive positive feedback is employed, alongside a stage which resets the membrane potential after a spike generation. The circuit was simulated with transistor models which account for parasitics effects and transient simulations for nA input synaptic currents are reported, with a peak current drawn from the power supply of 4 uA. The circuit operates on an accelerated timescale from units to tens of us, is equipped with external voltage biases to tune the membrane leak current, refractory period, and pulse width after silicon fabrication, hence suitable for developing mixed-signal neuromorphic architectures.
Stevenazzi, L., Baschirotto, A., De Matteis, M. (2025). Analog Integrate-And-Fire Neuron in 7 nm FinFET Technology. In 2025 International Conference on IC Design and Technology, ICICDT 2025 (pp.81-84). Institute of Electrical and Electronics Engineers Inc. [10.1109/ICICDT65192.2025.11077981].
Analog Integrate-And-Fire Neuron in 7 nm FinFET Technology
Stevenazzi L.;Baschirotto A.;De Matteis M.
2025
Abstract
In this work an analog Integrate-And-Fire Neuron is described and implemented in 7 nm FinFET technology. The circuit operates at a power supply voltage of 750 mV and features an operational-amplifier-based comparator to set an explicit spiking threshold voltage. A capacitive positive feedback is employed, alongside a stage which resets the membrane potential after a spike generation. The circuit was simulated with transistor models which account for parasitics effects and transient simulations for nA input synaptic currents are reported, with a peak current drawn from the power supply of 4 uA. The circuit operates on an accelerated timescale from units to tens of us, is equipped with external voltage biases to tune the membrane leak current, refractory period, and pulse width after silicon fabrication, hence suitable for developing mixed-signal neuromorphic architectures.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.


